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HCPL-2200, HCPL-2219
Low Input Current Logic Gate Optocouplers
Data Sheet
Description The HCPL-2200/2219 are optically coupled logic gates that combine a GaAsP LED and an integrated high gain photo detector. The detector has a three state output stage and has a detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. A superior internal shield on the HCPL-2219 guarantees common mode transient immunity of 2.5 kV/s at a common mode voltage of 400 volts. The Electrical and Switching Characteristics of the HCPL-2200/2219 are guaranteed over the temperature range of 0 C to 85 C and a VCC range of 4.5 volts to 20 volts. Low IF and wide VCC range allow compatibility with TTL, LSTTL, and CMOS logic and result in lower power consumption compared to other high speed optocouplers. Logic signals are transmitted with a typical propagation delay of 160 nsec. The HCPL-2200/2219 are useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments.
Features * 2.5 kV/s minimum Common Mode Rejection (CMR) at VCM = 400 V (HCPL-2219) * Compatible with LSTTL, TTL, and CMOS logic * Wide VCC range (4.5 to 20 V) * 2.5 Mbd guaranteed over temperature * Low input current (1.6 mA) * Three state output (no pullup resistor required) * Guaranteed performance from 0C to 85C * Hysteresis * Safety approval - UL recognized -3750 V rms for 1 minute - CSA approved - IEC/EN/DIN EN 60747-5-2 approved with VIORM = 630 V peak (HCPL-2219 Option 060 only) * MIL-PRF-38534 hermetic version available (HCPL-5200/1) Applications * Isolation of high speed logic systems * Computer-peripheral interfaces * Microprocessor system interfaces * Ground loop elimination * Pulse transformer replacement * Isolated buss driver * High speed line receiver
Functional Diagram
NC 1 ANODE 2 CATHODE 3 NC 4
8 VCC 7 VO 6 VE 5 GND
TRUTH TABLE (POSITIVE LOGIC) LED ENABLE OUTPUT ON H Z OFF Z H ON H L OFF L L
SHIELD
A 0.1 F bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide Minimum CMR dV/dt (V/s) 1,000 VCM (V) 50 Input OnCurrent (mA) 1.6 8-Pin DIP (300 Mil) Single Dual Channel Channel Package Package [1] HCPL-2200 HCPL-2201 HCPL-2202 HCPL-2231 [1] HCPL-2219 HCPL-2211 HCPL-2212 HCPL-2232 Small-Outline SO-8 Single Channel Package HCPL-0201 Widebody (400 Mil) Single Channel Package HCNW2201 Hermetic Single and Dual Channel Packages
2,500 5,000[2]
400 300[2]
1.8 1.6 1.6 1.8 2.0
HCPL-0211
HCNW2211
1,000
50
HCPL-52XX HCPL-62XX
Notes: 1. HCPL-2200/2219 devices include output enable/disable functionality. 2. Minimum CMR of 10 kV/s with VCM = 1000 V can be achieved with input current, IF, of 5 mA.
2
Ordering Information
HCPL-2200, HCPL-2219 are UL Recognized with 3750 Vrms for 1 minute per UL1577 and are approved under CSA Component Acceptance Notice #5, File CA 88324. Option Part RoHS non RoHS Number Compliant Compliant -000E no option HCPL-2200 -300E -300 -500E -500 -000E no option -300E -300 HCPL-2219 -500E -500 -060E -060 -360E -360 -560E -560
Package 300 mil DIP-8
Surface Mount X X
Gull Wing X X X X X X
Tape & Reel
UL 5000 Vrms/ 1 Minute rating
X
300 mil DIP-8 X X X X X
X
IEC/EN/DIN EN 60747-5-2 Quantity 50 per tube 50 per tube 1000 per reel 50 per tube 50 per tube 1000 per reel X 50 per tube X 50 per tube X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-2219-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant. Example 2: HCPL-2200 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant will use `-XXXE.'
Schematic
ICC 8 IF + VF - 2 IE 3 SHIELD 6 5 IO 7 VCC
VO VE GND
3
Package Outline Drawings 8-Pin DIP Package
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 5 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010)
OPTION CODE* DATE CODE
A XXXXZ YYWW RU 1 1.19 (0.047) MAX. 2 3 4
UL RECOGNITION
1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
5 TYP. 3.56 0.13 (0.140 0.005) 4.70 (0.185) MAX.
0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
1.080 0.320 (0.043 0.013)
0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010)
8-Pin DIP Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010)
8 7 6 5
1.016 (0.040)
6.350 0.25 (0.250 0.010)
10.9 (0.430)
1
2
3
4
1.27 (0.050)
2.0 (0.080)
1.19 (0.047) MAX.
1.780 (0.070) MAX.
9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
3.56 0.13 (0.140 0.005)
1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 0.25 (0.025 0.010)
12 NOM.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
4
Solder Reflow Thermal Profile
300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C
Regulatory Information The HCPL-2200/2219 have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. (Option 060 only)
TEMPERATURE (C)
200
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
ROOM TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Note: Non-halide flux should be used.
Recommended Pb-Free IR Profile
tp Tp TL
TEMPERATURE
TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC.
260 +0/-5 C 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C RAMP-DOWN 6 C/SEC. MAX.
Tsmax Tsmin
ts PREHEAT 60 to 180 SEC. 25 t 25 C to PEAK
tL
60 to 150 SEC.
TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C
Note: Non-halide flux should be used.
Insulation and Safety Related Specifications Parameter Min. External Air Gap (External Clearance) Min. External Tracking Path (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(IO1) L(IO2) Value 7.1 7.4 Units mm mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. DIN IEC 112/VDE 0303 Part 1
0.08
mm
CTI
200
V
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802. 5
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY)
Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 12, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V VIORM VPR Symbol Characteristic I-IV I-III 55/85/21 2 630 1181 V peak V peak Units
VPR
945
V peak
VIOTM
6000
V peak
TS IS,INPUT PS,OUTPUT RS
175 230 600 109
C mA mW
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-2, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
6
Absolute Maximum Ratings (No Derating Required up to 70C) Parameter Storage Temperature Operating Temperature Average Forward Input Current Peak Transient Input Current (1 s Pulse Width, 300 pps) Reverse Input Voltage Average Output Current Supply Voltage Three State Enable Voltage Output Voltage Total Package Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile
Symbol TS TA IF(AVG) IF(TRAN)
Min. -55 -40
Max. 125 85 10 1.0
Units C C mA A
Note 1
VR 5 V IO 25 mA VCC 0 20 V VE -0.5 20 V VO -0.5 20 V PT 210 mW 260C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings section
1
Recommended Operating Conditions Parameter Symbol Power Supply Voltage VCC Enable Voltage High VEH Enable Voltage Low VEL Forward Input Current IF(ON) Forward Input Current IF(OFF) Operating Temperature TA Fan Out N
Min. 4.5 2.0 0 1.6* - 0
Max. 20 20 0.8 5 0.1 85[1] 4
Units V V V mA mA C TTL Loads
*The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be used to permit at least a 20% CTR degradation guardband.
7
Electrical Specifications For 0C TA[1] 85C, 4.5 V VCC 20 V, 1.6 mA IF(ON) 5 mA, 2.0 V VEH 20 V, 0.0 V VEL 0.8 V, 0 mA IF(OFF) 0.1 mA. All Typicals at TA = 25C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified. See Note 7. Parameter Logic Low Output Voltage Logic High Output Voltage Output Leakage Current (VOUT > VCC) Logic High Enable Voltage Logic Low Enable Voltage Logic High Enable Current Logic Low Enable Current Logic Low Supply Current Logic High Supply Current High Impedance State Output Current Sym. VOL VOH IOHH VEH VEL IEH 0.004 IEL ICCL 4.5 5.25 ICCH 2.7 3.1 IOZL IOZH 2.0 0.8 20 100 250 -0.32 6.0 7.5 4.5 6.0 -20 20 100 500 25 40 IOSH -10 -25 IHYS VF BVR VF TA CIN 5 -1.7 0.12 1.5 1.7 1.75 Min. Typ. Max. Units 0.5 V V 100 500 A A V V A A A mA mA mA mA mA A A A A mA mA mA mA mA V V VEN = 2.7 V VEN = 5.5 V VEN = 20 V VEN = 0.4 V VCC = 5.5 V VCC = 20 V VCC = 5.5 V VCC = 20 V VO = 0.4 V VO = 2.4 V VO = 5.5 V VO = 20 V VO = VCC = 5.5 V VO = VCC = 20 V VCC = 5.5 V VCC = 20 V VCC = 5 V TA = 25C IR = 10 A IF = 5 mA IF = 5 mA, VO = GND 3 4 2 IF = 0 mA IO = Open VE = Don't Care IF = 5 mA IO = Open VE = Don't Care VEN = 2 V, IF = 5 mA VEN = 2 V, IF = 5 mA IF = 0 mA 2 Test Conditions IOL = 6.4 mA (4 TTL Loads) IOH = -2.6 mA VO = 5.5 V VO = 20 V *VOH = VCC - 2.1 V IF = 5 mA VCC = 4.5 V Fig. 1 2 Note
2.4
*
Logic Low Short Circuit Output Current Logic High Short Circuit Output Current Input Current Hysteresis Input Forward Voltage Input Reverse Breakdown Voltage Input Diode Temperature Coefficient Input Capacitance
IOSL
mV/C IF = 5 mA
60
pF
f = 1 MHz, VF = 0 V, Pins 2 and 3
8
Switching Specifications (AC) For 0C TA[1] 85C, 4.5 V VCC 20 V, 1.6 mA IF(ON) 5 mA, 0.0 mA IF(OFF) 0.1 mA. All Typicals at TA = 25C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified. Parameter Propagation Delay Time to Logic Low Output Level Propagation Delay Time to Logic High Output Level Output Enable Time to Logic High Output Enable Time to Logic Low Output Disable Time from Logic High Output Disable Time from Logic Low Output Rise Time (10-90%) Output Fall Time (90-10%) Sym. tPHL tPLH tPZH tPZL tPHZ tPLZ tr tf Min. Typ. 210 160 170 115 25 28 105 60 55 15 Max. Units ns 300 ns 300 ns ns ns ns ns ns Test Conditions Without Peaking Capacitor With Peaking Capacitor Without Peaking Capacitor With Peaking Capacitor Fig. 5, 6 5, 6 7, 9 7, 8 7, 9 7, 8 5, 10 5, 10 Note 4, 5 4, 5
Parameter Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity
Sym. |CMH|
Device HCPL-2200 HCPL-2219
Min. 1,000 2,500 1,000 2,500
Units V/s V/s V/s V/s
Test Conditions IF = 1.6 mA |VCM| = 50 V VCC = 5 V TA = 25C |VCM| = 400 V |VCM| = 50 V |VCM| = 400 V VF = 0 V VCC = 5 V TA = 25C
Fig. 11
Note 6
|CML|
HCPL-2200 HCPL-2219
11
6
Package Characteristics Parameter Input-Output Momentary Withstand Voltage* Input-Output Resistance Input-Output Capacitance Sym. VISO RI-O CI-O Min. 3750 Typ. Max. Units V rms pF Test Conditions RH 50%, t = 1 min., TA = 25C VI-O = 500 VDC f = 1 MHz, VI-O = 0 VDC Fig. Note 3, 8 3 3
1012 0.6
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage," publication number 5963-2203E.
9
Notes: 1. Derate total package power dissipation, PT, linearly above 70C free air temperature at a rate of 4.5 mW/C. 2. Duration of output short circuit time should not exceed 10 ms. 3. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 4. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the output pulse. The tPHL propagation delay is measured from the
50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing edge of the output pulse. 5. When the peaking capacitor is omitted, propagation delay times may increase by 100 ns. 6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V).
7. Use of a 0.1 F bypass capacitor connected between pins 5 and 8 is recommended. 8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 V rms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
IOH - HIGH LEVEL OUTPUT CURRENT - mA
VOL - LOW LEVEL OUTPUT VOLTAGE - V
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -60 -40 -20 0 20 40 60 80 100 VCC = 4.5 V IF = 0 mA VO = 6.4 mA
0
VO - OUTPUT VOLTAGE - V
5
VCC = 4.5 V IF = 5 mA VO = 2.7 V
-1 -2 -3 -4 -5 VO = 2.4 V -6 -7 -8 -60 -40 -20 0 20
VCC = 4.5 V TA = 25 C 4
3 IOH = -2.6 mA 2
1 IOL = 6.4 mA 0 0 0.5 1.0 1.5 2.0
40
60
80 100
TA - TEMPERATURE - C
TA - TEMPERATURE - C
IF - INPUT CURRENT - mA
Figure 1. Typical logic low output voltage vs. temperature.
Figure 2. Typical logic high output current vs. temperature.
Figure 3. Output voltage vs. forward input current.
PULSE GEN. tr = tf = 5 ns f = 100 kHz 10 % DUTY CYCLE VO = 5 V IF INPUT MONITORING NODE
VCC OUTPUT VO MONITORING NODE
HCPL-2200
1 2 3
5V D1 619
VCC 8
7 6
C2 = 15 pF 5 k
D2 D3 D4
1000
IF - FORWARD CURRENT - mA
R1
TA = 25 C 100 10 1.0 0.1 0.01 IF + VF -
4 C1 = 120 pF
GND 5
THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C1 AND C2. 2.15 k 1.10 k 681 RI 5 mA IF (ON) 1.6 mA 3 mA ALL DIODES ARE 1N916 OR 1N3064.
INPUT IF
1.2 1.3 1.4 1.5
0.001 1.1
IF (ON) 50 % IF (ON) 0 mA tPLH tPHL
VF - FORWARD VOLTAGE - V
OUTPUT VO
VOH 1.3 V VOL
Figure 4. Typical input diode forward characteristic.
Figure 5. Test circuit for tPLH, tPHL, tr, and tf.
10
250
tP - PROPAGATION DELAY - ns
200
VCC = 5 V C1 (120 pF) PEAKING CAPACITOR IS USED. SEE FIGURE 5.
IF (mA) 5 3 1.6
CL= 15 pF INCLUDING PROBE PULSE AND JIG CAPACITANCES. GENERATOR VCC ZO = 50 tr = tf = 5 ns VO HCPL-2200
1
+5 V
S1 D1 619
150
tPHL
1.6 3 5
VCC 8
7 6
IF
2 3
100
tPLH
CL 5 k
D2 D3 D4 S2
50 -60 -40 -20
4
GND 5
0
20
40
60
80 100
TA - TEMPERATURE - C
INPUT VC MONITORING NODE D1-4 ARE 1N916 OR 1N3064.
Figure 6. Typical propagation delays vs. temperature.
INPUT VE
tPZL 1.3 V
tPLZ 0.5 V 0.5 V 1.3 V 0V tPHZ
3.0 V 1.3 V 0V S1 AND S2 CLOSED VOL VOH 1.5 V S1 AND S2 CLOSED
OUTPUT S1 CLOSED VO S2 OPEN tPZH OUTPUT VO S1 OPEN S2 CLOSED
Figure 7. Test circuit for tPHZ, tPZH, tPLZ, and tPZL.
Tp - ENABLE PROPAGATION DELAY - ns
tP - ENABLE PROPAGATION DELAY - ns
100 CL = 15 pF 80
VCC 20 V 4.5 V
200
CL = 15 pF
tr, tf - RISE, FALL TIME - ns
120
VCC 150
tPHZ
100 80 60
VCC = 5 V C2 = 15 pF
20 V 4.5 V
60
tPLZ 20 V
100
40 tPZL 20 0 -60 -40 -20
4.5 V
tr
20 V 50
tPZH
40 20
tf
4.5 V
0
20
40
60
80 100
0 -60 -40 -20
0
20
40
60
80 100
0 -60 -40 -20
0
20
40
60
80 100
TA - TEMPERATURE - C
TA - TEMPERATURE - C
TA - TEMPERATURE - C
Figure 8. Typical logic low enable propagation delay vs. temperature.
Figure 9. Typical logic high enable propagation delay vs. temperature.
Figure 10. Typical rise, fall time vs. temperature.
11
OUTPUT POWER - PS, INPUT CURRENT - IS
HCPL-2200
A B 1 2 3
VCC OUTPUT VO MONITORING NODE 0.1 F BYPASS
800 700 600 500 400 300 200 100 0 0
HCPL-2219 OPTION 060 ONLY PS (mW) IS (mA)
VCC 8
7 6 5
RIN
VFF
4
GND VCM -
PULSE GENERATOR +
VCM 0V VOH OUTPUT VO VOL * SEE NOTE 6.
50 V SWITCH AT A: IF = 1.6 mA VO (MIN.)* SWITCH AT B: IF = 0 mA VO (MAX.)*
25
50
75 100 125 150 175 200
TS - CASE TEMPERATURE - C
Figure 12. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-2.
Figure 11. Test circuit for common mode transient immunity and typical waveforms.
VCC1 (+5 V)
VCC1 (+5 V) 1.1 k
120 pF HCPL-2200 1 2 VCC 8 7 6 GND 5
VCC2 (+5 V) DATA OUTPUT
1.1 k
120 pF (OPTIONAL*) HCPL-2200 1 2 VCC 8 7 6 GND 5
VCC2 (4.5 TO 20 V)
RL
CMOS
DATA OUTPUT
DATA INPUT TOTEM POLE OUTPUT GATE
1
3 TTL OR LSTTL 4
UP TO 16 LSTTL LOADS OR 4 TTL LOADS
DATA INPUT TOTEM POLE OUTPUT GATE
1
3 TTL OR LSTTL 4 VCC2 5V 10 V 15 V 20 V RL 1.1 K 2.37 K 3.83 K 5.11 K
2
2
Figure 13. Recommended LSTTL to LSTTL circuit.
Figure 14. LSTTL to CMOS interface circuit.
VCC (+5 V)
VCC1 (+5 V) 1.1 k 1 DATA INPUT TTL OR LSTTL D1 3 4 GND 6 5 2 HCPL-2200 VCC 8 7
120 pF (OPTIONAL*) 1.1 k 1 2 4.7 k HCPL-2200 VCC 8 7 6 GND 5
DATA INPUT OPEN COLLECTOR GATE
3 TTL OR LSTTL 4
D1 (1N4150) REQUIRED FOR ACTIVE PULL-UP DRIVER.
Figure 15. Recommended LED drive circuit.
Figure 16. Series LED drive with open collector gate (4.7 k resistor dhunts IOH from the LED).
*The 120 pF capacitor may be omitted in applications where 500 ns propagation delay is sufficient.
12
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2124EN AV01-0557EN July 5, 2007

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